The present invention relates to a display element driving device which is formed by cascade-connecting a plurality of driving circuits that drive a display element, such as a liquid crystal display element, based upon picture data signals, and concerns a display module using such a display element driving device.
FIG. 12 shows a system construction on the source side of a conventional display element driving device used in a liquid crystal display element. Here, the number of pixels of a liquid crystal panel serving as the liquid crystal display element is 800 pixelsxc3x973 (RGB) [source side]xc3x97600 pixels [gate side].
In the above-mentioned display element driving device, each of source drivers LSI (Large Scale Integrated Circuit) 101 serving as a plurality of driving circuits on the source side carries out a displaying operation with 64 gradations, and drives 100 pixelsxc3x973 (RGB). Therefore, the display element driving device on the source side is constituted by 8 source drivers LSI 101.
In the case when the eight source drivers LSI 101 have to be mutually distinguished, the source drivers LSI 101 at the respective 1 to 7 stages are referred to as the first to the seventh source drivers, and the source driver LSI 101 at the last stage is referred to as the eighth source driver.
Each source driver LSI 101 is packaged on a TCP (Tape Carrier Package) (not shown) and used. Here, in general, the TCP refers to a thin package made by bonding a driver LSI onto a film tape.
The above-mentioned display element driving device is provided with a controller 102. Respective voltages outputted from the respective output terminals, VLS, Vcc, GND and Vrefs 1 to 9, of the controller 102 are commonly supplied to the first to the eighth source drivers in parallel with each other. Moreover, various signals outputted from the respective output terminals, LS, Rxc2x7Gxc2x7B, SCK, of the controller 102 are also commonly supplied to the first to the eighth source drivers in parallel with each other. Here, a source driver starting pulse signal, outputted from an output terminal SSPI which will be described later, is successively transferred through the first to the eighth source drivers.
The following description will discuss flowing paths of the various signals released from the output terminals LS, Rxc2x7Gxc2x7B, SCK, SSPI of the controller 102.
First, signal conductors of picture data signals Rxc2x7Gxc2x7B (R, G, B, each having 6 bits) outputted from the output terminals Rxc2x7Gxc2x7B of the controller 102, a clock signal CK outputted from the output terminal SCK of the controller 102 and a latch signal LS outputted from the output terminal LS of the controller 102 are inputted to the first to the eighth source drivers in parallel with each other through respective common wires, Here, the source driver starting pulse signal SPI, outputted from the output terminal SSPI of the above-mentioned controller 102, is inputted to the input terminal SPin of the first source driver. The source driver starting pulse signal SPI thus inputted is transferred through the first source driver, and outputted from the output terminal SPout as a source driver starting pulse signal SPO. The source driver starting pulse signal SPO outputted from the first source driver is inputted to the input terminal SPin of the second source driver at the next stage as the source driver starting pulse signal SPI. Thereafter, in the same manner, the source driver starting pulse signal SPI is transferred up to the eighth source driver while being shifted.
Moreover, voltages, such as a power supply voltage Vcc for use in the source driver LSI 101, outputted from the output terminal Vcc of the controller 102, a ground connection electric potential GND electrically connected to the output terminal GND of the controller 102, 64 bit gradation displaying voltages Vrefs 1 to 9 outputted from the output terminals Vrefs 1 to 9 of the controller 102, a liquid crystal panel applying voltage adjustment voltage VLS outputted from the output terminal VLS of the controller 102, are supplied to the first to the eighth source drivers in parallel with each other through the respective common wires in the same manner as the above-mentioned flowing paths of the respective signals. Here, the power supply voltage Vcc, the ground connection electric potential GND, the 64 bit gradation displaying voltages Vrefs 1 to 9, and the liquid crystal panel applying voltage adjustment voltage VLS are, hereinafter, referred to as power-supply-related voltages.
Next, referring to a block diagram of FIG. 13, an explanation will be given of the circuit construction of the source driver LSI 101 shown in FIG. 12 and of the operations of the first to eighth source drivers, while also referring to timing charts of the various signals shown in FIG. 14.
As illustrated in FIG. 13, the source driver LSI 101 is constituted by a shift register 111, a data latch circuit 112, a sampling memory 113, a hold memory 114, a standard voltage generation circuit 115, a D/A converter 116 and an output circuit 117.
To the shift register 111 is inputted the source driver starting pulse signal SPI (see FIG. 14) outputted from the output terminal SSPI of the controller 102 through the input terminal SPin. The source driver starting pulse signal SPI is a signal synchronizing to the horizontal synchronizing signal of picture data signals Rxc2x7Gxc2x7B which will be described later. To the above-mentioned shift register 111 is inputted the clock signal CK (see FIG. 14) outputted from the output terminal SCK of the controller 102 through the first to the eighth source driver input terminals CKin.
By using the,source driver starting pulse signal SPI as a start pulse, the shift register 111 of the first source driver shifts the source driver starting pulse signal SPI in response to the first rise of the clock signal CK which has been inputted during the high level period of the source driver starting pulse signal SPI. The source driver starting pulse signal SPI, thus shifted, is outputted from the output terminal SPout of the first source driver as a source driver starting pulse signal SPO, and this is inputted to the input terminal SPin of the second source driver at the next stage. Thus, the source driver starting pulse signal SPI is shifted up to the eighth source driver at the final stage in the same manner.
Here, the picture data signals Rxc2x7Gxc2x7B, outputted from the output terminals Rxc2x7Gxc2x7B of the controller 102 consist of 6 bits respectively (see FIG. 14). As illustrated in FIG. 13, these picture data signals Rxc2x7Gxc2x7B are inputted to the data latch circuit 112 in parallel with each other from the input terminals R1 to 6in, G1 to 6in, B1 to 6in. After having been temporarily latched in the data latch circuit 112, the picture data signals Rxc2x7Gxc2x7B are supplied to the sampling memory 113. The above-mentioned picture data signals Rxc2x7Gxc2x7B are color digital picture signals consisting of R(Red), G(Green), B(Blue), each having 6 bits (total 18 bits).
The above-mentioned sampling memory 113 samples the picture data signals Rxc2x7Gxc2x7B that are sent through the output signals from the respective stages of the shift register 111 in a time divided manner, and stores them until a latch signal LS (outputted from the output terminal LS of the controller 102), which will be described later, is inputted.
Next, these picture data signals Rxc2x7Gxc2x7B are inputted to the hold memory 114. At the time when data corresponding to one level period of the picture data signals Rxc2x7Gxc2x7B has been inputted to the hold memory 114, they are latched by the latch signal LS inputted from the input terminal LSin. Up to the time when picture data signals Rxc2x7Gxc2x7B of the next level period have been inputted from the sampling memory 113 to the hold memory 114, the hold memory 114 holds the data of one level period of the picture data signals Rxc2x7Gxc2x7B, and then outputs this to the D/A converter 116. At this time, the shift register 111 and the sampling memory 113 carry out a data acquiring process on the picture data signals Rxc2x7Gxc2x7B of the next level period.
Based upon reference voltages that are outputted from the output terminals Vref 1 to 9 of the controller 102 and inputted to the input terminals Vref 1 to 9 of the first to eighth source drivers, the reference voltage generation circuit 115 generates voltages of 64 levels used for gradation display by using, for example, resistance division.
The D/A converter 116 converts the digital picture data signals Rxc2x7Gxc2x7B having 6 bits for R, G and B respectively into analog signals. Then, by using the liquid crystal panel applying voltage adjustment voltage VLS outputted from the output terminal VLS of the controller 102 and inputted to the input terminals VLS of the first to eighth source drivers, the output circuit 117 amplifies the analog signal of 64 levels, and outputs to the input terminals (not shown) of a liquid crystal panel through the output terminals XO 1 to XO 100, YO 1 to YO 100, and ZO 1 to ZO 100.
The above-mentioned output terminals XO 1 to XO 100, YO 1 to YO 100 and ZO 1 to ZO 100 respectively correspond to the picture data signals Rxc2x7Gxc2x7B requiring 100 terminals for R, G and B respectively. Here, the terminal Vcc and the terminal GND are power supply input terminals for supplying a power supply voltage Vcc and a ground connection electric potential GND to the first to eighth source drivers.
As described above, the display element driving device of the conventional display element driving device has a system on the source side in which: the eight source drivers LSI 101 packaged on TCPs are cascade-connected through the shift registers 111 and various signals and power-supply-related voltages are commonly supplied to the eight source drivers LSI 101.
In recent years, large screens have been developed by using liquid crystal panels, and in the case of the above-mentioned liquid crystal panel having 800 pixelsxc3x973 (RGB) [source side]xc3x97600 pixels [gate side], the clock signal on the source side requires approximately 60 MHz. When a plurality of source drivers LSI are operated by using such a high-speed clock signal, the power consumption extremely increases. Therefore, such an increase in the power consumption has come to impose a greater burden on the battery capacity in portable liquid crystal display devices.
In general, during a displaying operation of a liquid crystal display element, a plurality of driving circuits for driving the liquid crystal display element always receive signals transmitted from the controller, such as clock signals and display-use picture data signals. Therefore, in all the driving circuits, the inner logics are always operated, with the result that unnecessary charging and discharging electric currents are exerted, causing an increase in the power consumption.
In order to solve this problem, for example, Japanese Laid-Open Patent Application No. 72992/1993 (Tokukaihei 5-72992) and Japanese Laid-Open Patent Application No. 68949/1997 (Tokukaihei 9-68949) disclose methods for reducing power consumption by stopping the operation of an inner logic in an unnecessary driving circuit.
FIG. 15 shows the basic construction of a driving device disclosed in Japanese Laid-Open Patent Application No. 72992/1993 (Tokukaihei 5-72992). In this driving device, a control circuit 122 having a timing generation circuit is installed in each of a plurality of drivers 121i (i=1, 2, . . . , n) that are cascade connected, and when the control circuit 122 is operating a specific driver, signals such as clock signals and RGB signals to be inputted to the respective drivers 121i in parallel with each other are not supplied to the other drivers. This arrangement makes it possible to achieve low power consumption.
In FIG. 15, PDI represents a control signal to be inputted to a driver 1211, PDO represents a count-up output, STI represents a start pulse input signal, STO represents a start pulse output signal, L/R represents a shift direction instruction signal, and DS represents a start pulse input/output judgment control signal.
FIG. 16 shows the basic construction of a liquid crystal driving circuit constituting a liquid crystal driving device disclosed in Japanese Laid-Open Patent Application No. 68949/1997 (Tokukaihei 9-68949). In this liquid crystal driving device, a data buffer 132 with a data stop circuit that detects the period from the input to the output of the start signal of the shift register 131 so as to control the operation of the data buffer is installed. The data buffer 132 with the data stop circuit functions so that during an operation of a specific liquid crystal driving circuit, data signals (Rxc2x7Gxc2x7B signals), inputted to the respective liquid crystal driving circuits in parallel with each other, are not supplied to the other liquid crystal driving circuits. This arrangement makes it possible to achieve low power consumption.
In FIG. 16, STHL represents a cascade signal, STHR represents a start signal, CLK is a clock signal, R/L represents a shift direction switch signal, DR 0 to DR 7, DG 0 to DG 7, DB 0 to DB 7 represent display data, STB represents a latch signal, and V0 to V255 represent gradation level power supplies. Moreover, C1 to C80 represent inner signals from the shift register 131, and S1 to S240 represent gradation levels that are selected and outputted from gradation level power supplies V0 to V255.
Here, in recent years, there have been ever-increasing demands for low-cost, thin, light-weight, small-size, low-power-consumption apparatuses from the market for display modules such as liquid crystal display modules. For this reason, as one of the methods for responding to the above-mentioned demands, another method has been proposed in which, different from the conventional arrangement that supplies respective signals to a plurality of driving circuits in parallel with each other through common signal conductors, signal conductors are connected between driving circuits adjacent to each other so that the respective signals are supplied to the driving circuits.
As described above, since the respective signals are transmitted by using the signal conductors connecting the adjacent driving circuits, the length of the signal conductors is shortened so that the stray capacitance is reduced; thus, it becomes possible to provide high-speed operations and also to reduce the power consumption. Moreover, the application of this method makes it possible to eliminate externally added substrates (flexible substrates or printed substrates) required for placing the common signal conductors and consequently to greatly reduce the substrate area.
FIG. 17 shows one example of the system construction of a display element driving device on the source side in which the method for transmitting signals between the driving circuits as described above is adopted.
In the above-mentioned display driving circuit, not only the source driver starting pulse signal SPI, but also the picture data signals Rxc2x7Gxc2x7B having 6 bits respectively, the clock signal CK, the latch signal LS and power-supply-related voltages such as the power supply voltage Vcc, the ground connection electric potential GND, 64 bit gradation displaying voltages Vref 1 to 9 and the liquid crystal panel applying voltage adjustment voltage VLS, are transferred from the first source driver to the second source driver at the next stage by using the inner logics (inner circuits) of the eight source drivers LSI 141 or the inner wiring such as Al lines.
FIG. 18 is a block diagram that shows the circuit construction of the above-mentioned source driver LSI 141. Here, for convenience of explanation, those of the members that have the same functions as the members shown in FIG. 13 are indicated by the same reference numerals and the description thereof is omitted.
On one side of each source driver LSI 141 on the liquid crystal panel side are placed output terminals to the liquid crystal panel, XO 1 to 100, YO 1 to 100 and ZO 1 to 100. Moreover, on one side of each source driver LSI 141 on the controller 102 side are placed input terminals CKin, Rin, Gin, Bin and LSin for the clock signal CK, the picture data signals Rxc2x7Gxc2x7B having 6 bits respectively and the latch signal LS, and on one side opposing the controller 102 side are placed output terminals CKout, Rout, Gout, Bout and LSout for the above-mentioned respective signals.
Moreover, in the same manner, input terminals Vref 1 to 9, VLS, Vcc, GND for supplying the power-supply-related voltages such as the 64 bit gradation displaying voltages Vref 1 to 9, the liquid crystal panel applying voltage adjustment voltage VLS, the power supply voltage Vcc and the ground connection electric potential GND and output terminals Vref 1 to 9 out, VLS, Vcc and GND thereof are placed in the same manner as the input-output terminals of the respective signals. The respective power-supply-related voltages are used by connecting the respective voltage wires of Vcc, GND, Vref 1 to 9 and VLS lines to the respective two terminals, that is, the input terminals Vcc, GND, Vref 1 to 9in and VLS as well as the output terminals Vcc, GND, Vref 1 to 9out and VLS, through the inner wiring of the source driver LSI 141.
The above-mentioned input terminals and output terminals are connected by the inner wiring such as the Al line of each source driver LSI 141. FIG. 18 schematically shows a state in which these input terminals CKin, Rin, Gin, Bin, LSin, Vref 1 to 9in, VLS, Vcc and GND are connected to the output terminals CKout, Rout, Gout, Bout, LSout, Vref 1 to 9out, VLS, Vcc and GND by the inner wiring of the source driver LSI 141.
The source driver starting pulse signal SPI is inputted through the input terminal SPin, shifted by the shift register 111 inside the source driver LSI 141 synchronizing to the clock signal CK, and outputted from the output terminal SPout as the source driver starting pulse signal SPO.
The operation of each block of the source driver LSI 141 is carried out in the same manner as the aforementioned source driver LSI 101.
Moreover, FIG. 19 shows one example of the system construction of another source side display element driving device.
In the above-mentioned display element driving device, various signal conductors, which operate at high speeds, are connected between eight source drivers LSI 151, and the power-supply-related voltages are supplied to the respective source drivers LSI 151 in parallel with each other through the common wiring.
The above-mentioned arrangement makes it possible to achieve a low-cost, thin, light-weight, small-size display module such as a liquid display module. However, since this construction allows the inner logics to always operate in all the driving circuits, it fails to solve the problem of an increase in power consumption.
In a display element having a system construction which satisfies demands for low-cost, thinness, light-weight, small-size devices, that is, is free from an increase in the driving circuit scale, and which is capable of transferring picture data signals by using high-speed clock signals with a shortened wiring length obtained by cascade-connecting driving circuits so that picture data signals can be transmitted by using high-speed clock signals. The objective of the present invention is to provide a low-power-consumption display element driving device and a low-power-consumption display module using such a device that can meet demands for large screen panels.
In order to achieve the above-mentioned objectives, the display element driving device of the present invention is provided with: a plurality of driving circuits that drive a display element based upon picture data signals, and the driving circuit is provided with: a transfer section for shifting and transferring a start pulse signal that is cascade-connected between the driving circuits, synchronizing to a clock signal that is cascade-connected between the driving circuits; a selection section for selecting the picture data signals based upon the output of the transfer section; and a latch section for latching the picture data signals selected by the selection section by using a latch signal, is characterized in that each of the driving circuits is provided with an output control section which, up to the output of the start pulse signal to the driving circuit on the next stage or up to a predetermined time earlier than the output, stops the output of the clock signal to the driving circuit at the next stage.
With the above-mentioned arrangement, the output control section, which is installed in each of the driving circuits, stops the output of the clock signal up to the output of the start pulse signal or up to a predetermined period earlier than the output. In other words, the output control section outputs the clock signal to the driving circuit at the next stage simultaneously with the output of the start pulse signal to the driving circuit at the next stage or in the synchronized timing with a predetermined time earlier than the output. Therefore, no clock signal is inputted to the driving circuits at the next stage and thereafter that are not carrying out the acquiring operation of the picture data signals, with the transfer section, the selection section and the latch section being stopped in their operations.
In general, the cascade connection refers to a connection in which not less than two devices are connected so as to allow the output of one to serve as the input of another following the one. Therefore, when the clock signal and the start pulse signal are respectively cascade-connected between the driving circuits, these signals are successively transferred from one driving circuit to another driving circuit at the next stage connected to the one driving circuit.
As described above, in general, the transfer section, the selection section, the latch section, etc., which constitute a driving circuit, carry out high-speed operations. Therefore, when, in a driving circuit that needs not be operated, its transfer section, selection section, latch section, etc. are unnecessarily operated, there is a great increase in the power consumption.
In contrast, the application of the arrangement of the present invention makes it possible to stop unnecessary operations in the high-speed operating transfer section, selection section, latch section, etc. in the driving circuits that are not carrying out the acquiring operation of the picture data.
Moreover, the clock signal, which is a high-speed operating signal itself, is not inputted to the driving circuits at the next stage and thereafter that need not be operated; therefore, it is not necessary to carry out charging and discharging for stray capacitances resulting from the external wiring placed outside the driving circuits for transmitting the clock signal, the external substrates on which the external wiring is placed, etc.
Thus, it is possible to greatly cut the power consumption required for carrying out high-speed operations in the transfer section, the selection section, the latch section, etc. in the driving circuits that need not be operated as well as the power consumption required for charging and discharging the stray capacitances of the external wiring, etc., and consequently to achieve low power consumption in the display element driving device.
Moreover, at least the above-mentioned clock signal and start pulse signal are allowed to transmit through the driving circuits while being cascade-connected between the driving circuits; therefore, since the clock signal and the start pulse signal are supplied in parallel with the respective driving circuits, no external wiring is required.
This arrangement makes it possible to reduce the number of external wires, thereby achieving miniaturization of the display element driving device. Moreover, the externally attached substrates for placing external wires can be miniaturized or eliminated so that further miniaturization of the display element driving device is achieved.
Furthermore, the display element driving device of the present invention is characterized in that the picture data signals are cascade-connected between the respective driving circuits, and in that the output control section stops the output of the picture data signal to the driving circuit at the next stage up to the output of the start pulse signal to the driving circuit at the next stage or up to a predetermined time earlier than the output
With this arrangement, the image data signals are also cascade-connected between the driving circuits in the same manner as the clock signal. Moreover, the output control section controls the output to the driving circuit at the next stage also with respect to the picture data signals. In other words, the output control section stops the output of the picture data signal up to the output of the start pulse signal or up to a predetermined time earlier than the output.
The picture data signals as well as the clock signal are not outputted to the driving circuits at the next stage and thereafter that are not carrying out the acquiring operation of the picture data signals; therefore, it is not necessary to carry out charging and discharging for stray capacitances resulting from the external wiring placed outside the driving circuits, the externally attached substrates on which the external wiring is placed, etc. Moreover, in the driving circuits at the next stage and thereafter, it is possible to cut unnecessary power consumption, for example, required for the operation between the input buffer for the picture data signals and the circuit for temporarily latching the picture image data signals.
Thus, it is possible to greatly cut the power consumption required for carrying out high-speed operations of the driving circuits that need not be operated as well as the power consumption required for charging and discharging the stray capacitances of the external wiring, etc., and consequently to achieve low power consumption in the display element driving device.
Moreover, a display module in accordance with the present invention has a display element driving device that is provided with: a plurality of driving circuits that drive a display element based upon picture data signals, and the driving circuit is provided with: a transfer section for shifting and transferring a start pulse signal that is cascade-connected between the driving circuits, synchronizing to a clock signal that is cascade-connected between the driving circuits; a selection section for selecting the picture data signals based upon the output of the transfer section; and a latch section for latching the picture data signals selected by the selection section by using a latch signal, and that is characterized in that each of the driving circuits is provided with an output control section which, up to the output of the start pulse signal to the driving circuit on the next stage or up to a predetermined time earlier than the output, stops the output of the clock signal to the driving circuit at the next stage, and also has a display element driven by the above-mentioned display element driving device.
Furthermore, another display module in accordance with the present invention has a display element driving device that is provided with: a plurality of driving circuits that drive a display element based upon picture data signals, and the driving circuit is provided with: a transfer section for shifting and transferring a start pulse signal that is cascade-connected between the driving circuits, synchronizing to a clock signal that is cascade-connected between the driving circuits; a selection section for selecting the picture data signals that are cascade-connected between the driving circuits, based upon the output of the transfer section; and a latch section for latching the picture data signals selected by the selection section by using a latch signal, and that is characterized in that each of the driving circuits is provided with an output control section which, up to the output of the start pulse signal to the driving circuit on the next stage or up to a predetermined time earlier than the output, stops the output of the clock signal to the driving circuit at the next stage, and also has a display element driven by the above-mentioned display element driving device.
In the above-mentioned arrangements, the display element driving device, which has achieved a reduction in the power consumption and has been miniaturized, drives the display element in the display module.
Consequently, it is possible to provide a display module which achieves a weight reduction, thinness, miniaturization and low costs.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.